Apple Cellular SOC Design Verification Engineer in Austin, Texas
Cellular SOC Design Verification Engineer
5+ years of dedicated/hands-on ASIC DV experience.
Advanced knowledge of HVL methodology (UVM/OVM) with most recent experience in UVM.
Proven track record of working full ASIC cycle from concept to tape-out to bring-up.
Experience taping out large SOC systems with embedded processor cores.
Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.
Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.
• Understand details of High Efficiency SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, DDR, Memory Controller Sub Systems, USB, PLL, power up, Secured Boot schemes. • Create coverage driven verification plans from specifications, review and refine to achieve coverage targets. • Create IP level module and sub-system verification plan, TB, portable test benches, sequences, test infrastructure. • Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level, achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify overall SOC design. • Work closely with DV methodology architects to improve verification flow.
Education & Experience
Typically requires MSEE with 5+ years of verification experience.
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