Intel High Speed Serial IO Validation Engineer in Austin, Texas
In this position you will be part of the Intel iVE high speed IO validation team responsible for the electrical validation of high-speed serial interfaces to ensure compliance with industrial requirements and healthy system margins. This position requires close work with Circuit Design, Manufacturing, BIOS, Board development teams, PLL manufacturing validation and firmware engineers, Applications engineers, Simulation and Validation teams.
Responsibilities will include but not be limited to:
Validate and debug system clocks and associated PLLs at a system level
Develop and documents electrical validation requirements and tests for verification of signal integrity designs
Validate system IO margins to assess product quality and make product release recommendations
Integrate circuit debug and validate guarantee I/O margin to spec
Validate characteristics of high-speed serial interfaces such as PCIe
Develop scripts, software to validate the circuit parameters
Analysis of I/O specification versus performance to ensure optimal match of design requirements
Participate in developing new processes and validation methodologies and improve existing processes and validation methodologies
Correlate high volume manufacturing tests limits to electrical validation
Work as a peer leader in a team-oriented environment and interacting with engineers from cross functional teams and sites
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
The candidate must possess a Bachelor's degree in Electrical Engineering with 3+ years of experience or a Master's degree in Electrical Engineering with 2+ years of experience with:
Software coding and debug skills (Python, Matlab, C++, other)
Signal integrity and transmission line theory
Hands-on lab/debug experience with measurement and debug tools such as DMMs, oscilloscopes and BERT
Validation methodologies and development
Platform Architecture experience (IO, Power delivery)
PLL, crystal oscillators, general clocking experience or power management involving PLL relocking
Experience with analog IO & platform debug
Experience with IO protocols, specs and compliance testing (PCI Express, SATA, USB3, DDR etc.) is highly desired
Experience with statistical analysis and risk assessment for quality assessments is a plus
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....
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